Arguably the most valuable insight from the past few days of memory industry news came from Lam Research CEO Tim Archer. On the company’s October 21, 2026 earnings call, Archer explained that the growing adoption of SLC NAND for AI could increase the wafer capacity needed to supply the same amount of storage. Let’s take a closer look. Specifically, moving from TLC to SLC-class products reduces the number of bits stored per cell to roughly one-third. As a result, he said, every 1-percentage-point increase in SLC’s share of total NAND bits would require approximately 2% more wafer capacity to meet the same overall bit demand. Some readers may wonder whether SLC is an outdated approach to NAND production, used mainly in legacy products. Far from it. SLC is a highly promising area that could play a role in NAND similar to the one HBM plays in DRAM. NAND customers, including NVIDIA and the hyperscalers, are developing next-generation products based on SLC. Within the NVIDIA ecosystem, the focus is on SLC-based XL-Flash, also known as high-IOPS NAND. Outside the NVIDIA ecosystem, SLC is also being used as the basis for HBF. Put simply, matching the storage capacity of one TLC wafer requires roughly three SLC wafers, while matching one QLC wafer requires roughly four. As production of these SLC-based products ramps up, they will consume an increasing amount of NAND wafer capacity. Just as HBM drove shortages in DRAM, these products could create a similar dynamic in NAND. With HBF and XL-Flash scheduled to enter volume production in 2028 and 2027, respectively, I think we should consider whether some analysts’ forecasts of NAND prices beginning to decline in the fourth quarter of 2027 may be overly conservative.