🎙️ NEW EPISODE: How Intel Took EMIB From Science Fiction to High Volume: Intel Foundry's Ravi Mahajan Ravi Mahajan, a distinguished engineer at Intel Foundry, joins Austin to detail EMIB's 20-year journey from a "science fiction" concept to a high-volume manufacturing reality. - Organic package wire escape density at the die edge improved only about 10% per generation, so EMIB puts fine-pitch silicon in small patches at the die edges and leaves power to the substrate's thick metal - Production required five technologies to converge, including a custom 4-layer silicon process and dies half the thickness of an A4 sheet of paper - HBM was the first driver. Solve the highest-performance memory interconnect and the technology can "waterfall down" to everything else - The advantage over CoWoS is manufacturing scale. Small bridges replace a full-sized silicon interposer and its high cost and poor wafer utilization on large, multi-reticle AI packages - EMIB-T was in the original patent, using TSVs to fix the "torturous" power path around the bridge - EMIB is an Intel Foundry exclusive, and the roadmap includes top-side optics This episode is presented by @CrusoeAI. Crusoe's Serverless Fine-Tuning trains an open model like Llama, DeepSeek, or GLM on your own data, and you pay per million tokens, not per GPU hour. About $2 buys roughly 5M training tokens on smaller models. Get $5 in credit to start: semidoped.com/crusoe-x Chapters: 0:00 Intro: Ravi Mahajan 1:44 Pathfinding & The HIR Roadmap 7:58 The Two Drivers of EMIB 15:15 Decoupling I/O and Power 16:27 The 'Science Fiction' of EMIB 20:36 HBM as the Killer App 25:06 EMIB vs. CoWoS 31:44 Chiplets, UCIe, and Packaging Tiers 34:08 The EMIB Portfolio: T, M, Active 37:01 An Intel Foundry Exclusive 41:21 AI's Role in Packaging 43:26 Future: Top-Side Optics Get more of Austin and Vik daily, free! Sign up: daily.semidoped.com/ Connect with Vik and Austin: Vik's Paid Substack: viksnewsletter.com Austin's Paid Substack: chipstrat.com @austinsemis @vikramskr @Intel_Foundry