@WillFlux

Only hardware makes it possible! FPGA, RISC-V, 68K, OS, graphics, demos, permacomputing 🦣 https://xitter.cf/t.co/hoDeBTqKT0

 St Leonards-on-Sea, England
projectf.io
Joined May 2013
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Isle 🏝️ is my new #FPGA project. Isle is a simple, modern computer — an open design that encourages tinkering, experimentation, and doing your own thing. I hope to inspire you to come on a journey with me and build your own computer. projectf.io/isle/fpga-comput…
A coconut sapling on a tropical beach.

ALT A coconut sapling on a tropical beach.

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Some pre-Christmas tidying on Isle #FPGA Computer: add more tests, upgrade to cocotb 2.0, resolve all Yosys warnings, resolve all pylint warnings, add Arch Linux instructions, better Makefiles... I hope Father Christmas appreciates this. 🎅 github.com/projf/isle

GitHub - projf/isle: Isle FPGA Computer

Isle FPGA Computer. Contribute to projf/isle development by creating an account on GitHub.

github.com
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Quick Isle update. You can now choose Unscii for the text mode font ROM. Unscii was designed by Viznut based on classic system fonts.
Isle text mode with Unscii font showing block and Latin characters.

ALT Isle text mode with Unscii font showing block and Latin characters.

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Now text mode is live, I thought I should update my discussion of Isle computer display modes and resolutions projectf.io/isle/display-mod… It's tempting to keep experimenting with new resolution and colour depth combos, but I'm sticking to my current design. 😅
Table showing the different Isle display, bitmap, and text mode resolution combinations. You can read the full table in the tweet link (it's difficult to format tables in alt text).

ALT Table showing the different Isle display, bitmap, and text mode resolution combinations. You can read the full table in the tweet link (it's difficult to format tables in alt text).

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Another cool ULX3S project: xitter.cf/i/status/1999538187513…
Flux@WillFlux12 Dec 2025
Isle computer hardware text mode is now live. Have a play and let me know how you get on. #FPGA Blog: projectf.io/isle/text-mode.h… Code: github.com/projf/isle
ULX3S FPGA dev board connected to widescreen monitor showing test text in 16 colours.

ALT ULX3S FPGA dev board connected to widescreen monitor showing test text in 16 colours.

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Isle computer hardware text mode is now live. Have a play and let me know how you get on. #FPGA Blog: projectf.io/isle/text-mode.h… Code: github.com/projf/isle
ULX3S FPGA dev board connected to widescreen monitor showing test text in 16 colours.

ALT ULX3S FPGA dev board connected to widescreen monitor showing test text in 16 colours.

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Isle computer supports @machdyne Lakritz, @DigilentInc Nexys Video, and @RadionaOrg #ULX3S. And it's easy to run Isle's simulation; for example on macOS with brew installed: brew install verilator sdl2 cd isle/boards/verilator/ch04 make ./obj_dir/ch04 # run sim
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Isle is open hardware and uses an open-source toolchain (Yosys & nextpnr) for ECP5 #FPGA. With the toolchain installed, it's quick and simple to get Isle running. For example, text mode (chapter 4) on ULX3S: cd isle/boards/ulx3s/ch04 make openFPGALoader --board ulx3s ch04.bit
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I've accidentally started reading about flood fill algorithms. Span filling looks doable in a reasonable amount of logic and memory (for non-pathological shapes). I'm almost tempted to give it a go in #Verilog over Christmas.🎄
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I realised my weird Verilog text mode rendering issues were caused by swapping to a memory module with an output reg. Premature optimisation and off-by-one error! 😅 🏝️Isle #FPGA computer text mode supports Unicode with 16 foreground and background colours using GNU Unifont.
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Isle text mode hardware supports separate X and Y scaling. #FPGA
Text mode with x-scale=1 and y-scale=1 in Verilator/SDL simulation. 84x24 half-width glyphs.

ALT Text mode with x-scale=1 and y-scale=1 in Verilator/SDL simulation. 84x24 half-width glyphs.

Text mode with x-scale=3 and y-scale=2 in Verilator/SDL simulation. 28x12 half-width glyphs.

ALT Text mode with x-scale=3 and y-scale=2 in Verilator/SDL simulation. 28x12 half-width glyphs.

Text mode with x-scale=6 and y-scale=4 in Verilator/SDL simulation. 14x6 half-width glyphs.

ALT Text mode with x-scale=6 and y-scale=4 in Verilator/SDL simulation. 14x6 half-width glyphs.

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Isle.Computer hardware text mode on #ULX3S. With 2x scaling and horizontal offset to centre at 1366x768. I’m getting ready to release the next chapter and hardware designs. #FPGA
ULX3S FPGA dev board connected to widescreen monitor showing test text in 16 colours.

ALT ULX3S FPGA dev board connected to widescreen monitor showing test text in 16 colours.

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Yesterday, I discovered a 959416035780 byte log file on a client server. Enough space to write a tweet about every year the Universe has existed.
The Hubble Deep Field, a picture taken over the course of ten consecutive days in December 1995, by the Hubble Space Telescope.

ALT The Hubble Deep Field, a picture taken over the course of ten consecutive days in December 1995, by the Hubble Space Telescope.

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959416035780 bytes would fill over one million Amiga floppy disks. 💾
The author's Amiga 500, AMOS, and Deluxe Paint II floppy disks in a grey Commodore floppy disk wallet.

ALT The author's Amiga 500, AMOS, and Deluxe Paint II floppy disks in a grey Commodore floppy disk wallet.

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If you're writing assembler, I heartily recommend Compiler Explorer. I wrote about this from a RISC-V perspective a while back. #asm #riscv projectf.io/posts/riscv-comp…
Screenshot of Compiler Explorer showing C source for endian swap function being compiled into RISC-V asm with Clang 18.1.

ALT Screenshot of Compiler Explorer showing C source for endian swap function being compiled into RISC-V asm with Clang 18.1.

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Compiler Explorer is a great way to understand the effect of #riscv extensions or compare CPU arch. You can even compare rv32 and armv7 to a 486. 🤔 For example, an endian swap takes 11 instructions with the base RISC-V ISA, but only 1 instruction (rev8) with the Zbb extension.
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🏝️ Isle #FPGA Computer now has a Verilog 2D graphics engine. Blog: projectf.io/isle/2d-drawing.… Code: github.com/projf/isle
Monitor attached to FPGA dev board (out of shot) displaying Earthrise all shapes demo with lines, triangles, circles, rectangles, and squares in greens, oranges, and yellows.

ALT Monitor attached to FPGA dev board (out of shot) displaying Earthrise all shapes demo with lines, triangles, circles, rectangles, and squares in greens, oranges, and yellows.

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🏝️Earthrise 2D graphics hardware uses a custom 16-bit instruction set. I've written a reference guide and assembler tool to make programming (relatively) easy. #FPGA Programming reference: github.com/projf/isle/blob/m…
The machine for each instruction (in hex format) looks like this: 0xC00A # lca 10 0xC108 # lcb 8 0x0008 # x0 8 0x1010 # y0 16 0x2010 # x1 16 0x3018 # y1 24 0xD100 # draw line ca 0x1020 # y0 32 0xD102 # draw line cb 0xCE00 # stop (CEase)

ALT The machine for each instruction (in hex format) looks like this: 0xC00A # lca 10 0xC108 # lcb 8 0x0008 # x0 8 0x1010 # y0 16 0x2010 # x1 16 0x3018 # y1 24 0xD100 # draw line ca 0x1020 # y0 32 0xD102 # draw line cb 0xCE00 # stop (CEase)

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If you have a @machdyne Lakritz, @DigilentInc Nexys Video, or @RadionaOrg ULX3S #FPGA board, please give the latest 🏝️Isle design a test and let me know how you get on. 🙏 2D drawing blog post: projectf.io/isle/2d-drawing.… FPGA board Support: github.com/projf/isle/tree/m…
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