A research lab for the next era of silicon design
San Francisco, CA
Joined March 2026
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🥳🥳🥳
Thrilled to announce that @naveen_venk and I have joined @joinef to build @archgen_ .
Our thesis is simple:
The next generation of semiconductor design tools will not just automate workflows they will learn from every engineer who uses them.
Chip design today is full of repeated manual effort.
1. A senior physical design engineer fixes a timing issue.
2. Another engineer solves a congestion problem.
3. Someone else discovers a better macro placement strategy.
4. A team spends weeks tuning PPA across hundreds of experiments.
But most of this knowledge disappears into scripts, logs, webex threads, reports, and individual engineer's memory.
We’re changing that.
At @archgen_ , we’re building self-learning agents for semiconductor design, with specific focus on physical design.
Our agents work alongside engineers, run EDA flows, inspect reports, debug failures, optimize PPA, and capture the reasoning behind successful workflows.
1. When an engineer solves something, the agent learns.
2. When a strategy fails, the agent remembers why.
3. When a similar problem appears again, the agent can reuse the right approach.
Over time, this becomes an organisational memory layer for chip design. One that compounds.
Our vision is to make chip design feel less like manually stitching together fragmented tools and more like working with a team of expert agents that get better every day.
The future of semiconductor design is self-learning.
Huge thanks to @suhasasumukh 🐐 and @localhosthq for being extremely generous with their credits and supporting us throughout.
#semiconductors #EDA #physicaldesign #ASIC #chipdesign #AI
Archgen Labs (YC F26) retweeted
Was insightful listening to PG, Jessica and Garry talk about the OG YC batches
@paulg @jesslivingston @garrytan @ycombinator
Archgen Labs (YC F26) retweeted
Is it a chip? Is it a wafer?
It’s Cerebras Wafer Scale Engine.
@cerebras
#semiconwest
Archgen Labs (YC F26) retweeted
A little late, but excited to finally share this.
@archgen_ is backed by @ycombinator
Chip design needs a new stack for the 3D era. We’re building it at @archgen_ .
If you’re working in semiconductors, we’d love to grab a coffee.
Archgen Labs (@archgen_) is now backed by Y Combinator (@ycombinator)
We are a research lab for silicon design, with one ambition: make chip design 1,000× faster.
For decades, computing advanced by shrinking transistors. The next chapter for compute workloads will increasingly depend on building vertically - stacking active logic layers to create 3D chips.
This makes designing those chips much harder but also opens up new possibilities for performance and efficiency.
At @archgen_ , we’re bringing together foundational models, EDA tools, and physics-informed surrogate models to explore more designs, predict their behavior faster, and optimize how they’re built.
Grateful to Kulveer Taggar (@kul), Garry Tan (@garrytan) and the @ycombinator team for backing us, and to the customers, mentors, and collaborators who have helped us get here.
If you want to get to tapeout faster, we’d love to talk. DM us.
#Semiconductors #OpenROAD #OpenLane #OpenSourceEDA #ChipDesign #VLSI #PhysicalDesign #AIForHardware #3DIC
@naveen_venk
Archgen Labs (YC F26) retweeted
hippodupac caught me cold approaching @paulg
Archgen Labs (YC F26) retweeted
@mercatus was one of the earliest believers in us.
At the time, @naveen_venk and I had no product, no customers and very little money.
We were two twenty-somethings with a thesis: AI could fundamentally change how chips are designed.
Most people did not believe us. But @srajagopalan and emergent ventures did.
Their $15,000 grant allowed us to incorporate @archgen_ , keep building and gain access to the GCP credits we needed to run our early experiments.
That compute helped us develop the optimization system that eventually ranked #1 in the Macro Placement Challenge from @WeAreHRT and Partcl
That first check was more than capital. It gave us time, credibility and the confidence to continue before there was much evidence that we would succeed.
Today, @archgen_ is backed by @ycombinator
We are still pursuing the same belief: chip design can become dramatically faster through AI.
Thank you, @srajagopalan and @tylercowen for believing before it was obvious.
Archgen Labs (YC F26) retweeted
Some of the AI chip design nerds at Semicon #SEMICONWest
@RithikWasHere @kevingubbi @naveen_venk @RahulBhagwat01
Archgen Labs (YC F26) retweeted
Any sufficiently advanced engineering is indistinguishable from magic
Archgen Labs (YC F26) retweeted
@lossfunk is one of the highest-talent-density startup communities in the world.
It has been an important part of our journey at @archgen_ , and we're grateful to @paraschopra, @ Jay Joshi and @whyloop_ for the energy they have invested in bringing ambitious builders together.
Thank you to the entire Lossfunk community for creating this in Bangalore. Excited to see what comes out of it next!!
@naveen_venk
Some exciting updates!
A bunch of @lossfunk residents have raised funding + a few Lossfunk incubated companies have received $25k each in Google Cloud compute credits. More details below 👇
---
@HariAyapps, who's building @archgen_, got into YC W26 🥳🥳
Residents who started building at Lossfunk got into @joinef S26: the @oruel_inc team (@chastronomic, @prb5h, @nihipap) and @suryamaddula_ building @WhisperwaveAI
Former Lossfunk researcher @harshablast started Dirac Robotics as part of @joinef S26
---
A total of $175,000 in compute credits has already been disbursed to 7 Lossfunk-incubated companies, and 9 more are in the process of receiving them.
Thanks, @googlecloud, for the credits.
• athenaagent: @sachdh
• attenor: @ViraajG1
• autr: @V_J_S_1
• fpvlabs: @levelheaded_94
• grit: @timbresociety
• prometei: @navbenny
• scoutfox
Archgen Labs (YC F26) retweeted
@naveen_venk and I finally met our maker today
Thank you so much @srajagopalan @tylercowen and the @mercatus team for believing in young founders with crazy ideas. At 24 we are probably the oldest founders at @mercatus xD
Unparalleled talent density at emergent ventures
Archgen Labs (YC F26) retweeted
Thank you to everyone who attended the first-ever @hackerfabindia × @archgen_ session on semiconductors design and fabrication at LocalHost HQ last week!
More than 50 people joined us to explore how open-source initiatives such as openROAD and the Open-Source FPGA Foundation are helping democratize custom semiconductor design and fabrication.
A special thank-you to @aryamman_bhatia for taking time out of his incredibly busy schedule to explain how people can build their own fabs, even without cleanrooms, massive capital investments, or traditional infrastructure.
Huge thanks as well to @suhasasumukh for hosting us at @localhostIND.
@naveen_venk and I had a fantastic time discussing open-source chip design and sharing how Archgen AI is helping grow the community through our agentic EDA systems.
#Semiconductors #OpenSourceEDA #ChipDesign #HackerFab #VLSI #AgenticEDA
Archgen Labs (YC F26) retweeted
@naveen_venk and I had an awesome chat with @aryamman_bhatia about how chip design can be made more accessible and open.
Would love to share some of our learnings over coffee tomorrow on how you can build your own semiconductor chip. Do register!!
@archgen_ @hackerfabindia
Organising a meetup, with @HariAyapps @naveen_venk to discuss the work we’re doing @hackerfabindia and @archgen_ as well as semiconductors in general.
If you’re in BLR at 7pm, 9th Aug and interested in semiconductors- you should definitely drop by.
luma.com/jw1cwxxw
Archgen Labs (YC F26) retweeted
Such a cool informative session on "How to build a semiconductor chip?" by our friends @HariAyapps and @naveen_venk at Archgen(@archgen_) with @aryamman_bhatia from HackerFab(@hackerfabindia).
Archgen Labs (YC F26) retweeted
Got a chance to host @aryamman_bhatia at @lossfunk.
We talked about what it'll really take to design and fabricate cutting edge semiconductors from india
Archgen Labs (YC F26) retweeted
On our way to @lossfunk to talk about how to use AI to design better semiconductor chips!!!
Archgen Labs (YC F26) retweeted
We built the best chip design engine in the world!! 🥳🥳
@archgen_ is currently ranked #1 on the @WeAreHRT / Partcl Macro Placement Challenge 2026 leaderboard.
Macro placement is one of the hardest problems in physical design.
It involves placing large fixed-size blocks such as SRAMs, IPs, and analog macros on a chip floorplan while balancing, wirelength, density, congestion, routability, timing and constraints.
After months of research and iteration our submission reached a verified rank-1 with an average proxy cost of 0.9507 across the IBM benchmark suite.
@naveen_venk and @JishnuMada86596 burned the midnight oil to build an optimization flow that combined fast local repair, multi-start search, congestion-aware ranking, GPU-accelerated candidate generation and strict legality checks to reach the top spot. (detailed blog in the comments)
Grateful to Madhusudan S, Abhishek Lal, and Anant Gulati for their valuable suggestions and inputs to help us overcome issues in EDA algorithms, traditional macro placement algorithms and GPU optimisation.
If you are working on physical design and want to understand how AI, self learning agents, loops, and GPU-accelerated optimisation can improve your flows please feel to reach out to us.
Thank you @Willschips, Vamshi Balanaga and the Partcl team for organising this competition.
#PhysicalDesign #EDA #ChipDesign #VLSI #AIforEDA #Semiconductors #Placement #ArchGen #HardwareDesign
Archgen Labs (YC F26) retweeted
Excited to share that Team @archgen_ is currently ranked #1 in the Hudson River Trading (HRT) & Partcl Macro Placement Challenge, competing against 120+ teams from across the globe for the 20K USD first-place prize.
This achievement is the result of an incredible team effort by @HariAyapps & @JishnuMada86596 . Thank you for the countless hours, relentless experimentation, and commitment to pushing through every challenge along the way.
The journey was anything but easy. It involved sleepless nights, failed experiments, endless debugging sessions, and constantly challenging our assumptions. Many ideas looked promising at first, only to be replaced by something better after another round of testing. Through it all, the team kept pushing forward.
Also grateful to Madhusudan S , Abhishek Lal , Anant Gulati who helped us refine ideas, challenge our thinking, and navigate roadblocks throughout the competition. Your feedback and support made a real difference.
Our prior contributions to OpenROAD and the open-source ecosystem gave us a strong starting point, but the real progress came from the team's ability to rapidly iterate, measure, and improve.
We've shared the technical details behind our approach in the article below.
At Archgen, we're building AI-powered engineering systems to help accelerate chip design and bring ideas to silicon faster.
If you're interested in macro placement, AI for physical design, or EDA in general, we'd be happy to discuss the work in more depth. We'll also be at DAC (Design Automation Conference) this July, so feel free to reach out if you'd like to connect and chat in person.
Thanks @Willschips , Vamshi and Partcl for organizing this competition.
#Archgen #EDA #OpenROAD #PhysicalDesign #Semiconductors #VLSI #ChipDesign #AI #DAC
Archgen Labs (YC F26) retweeted
Thrilled to announce that @naveen_venk and I have joined @joinef to build @archgen_ .
Our thesis is simple:
The next generation of semiconductor design tools will not just automate workflows they will learn from every engineer who uses them.
Chip design today is full of repeated manual effort.
1. A senior physical design engineer fixes a timing issue.
2. Another engineer solves a congestion problem.
3. Someone else discovers a better macro placement strategy.
4. A team spends weeks tuning PPA across hundreds of experiments.
But most of this knowledge disappears into scripts, logs, webex threads, reports, and individual engineer's memory.
We’re changing that.
At @archgen_ , we’re building self-learning agents for semiconductor design, with specific focus on physical design.
Our agents work alongside engineers, run EDA flows, inspect reports, debug failures, optimize PPA, and capture the reasoning behind successful workflows.
1. When an engineer solves something, the agent learns.
2. When a strategy fails, the agent remembers why.
3. When a similar problem appears again, the agent can reuse the right approach.
Over time, this becomes an organisational memory layer for chip design. One that compounds.
Our vision is to make chip design feel less like manually stitching together fragmented tools and more like working with a team of expert agents that get better every day.
The future of semiconductor design is self-learning.
Huge thanks to @suhasasumukh 🐐 and @localhosthq for being extremely generous with their credits and supporting us throughout.
#semiconductors #EDA #physicaldesign #ASIC #chipdesign #AI