@zipcpu

FPGA design engineer and blogger, placing particular emphasis on test and formal verification

 Gisselquist Technology, LLC,
zipcpu.com
Joined January 2017
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Wow, lots of new twitter followers just joined. Welcome! Just to give you an opportunity to get to know me and the ZipCPU blog, here's a bit about me and what you can expect here: zipcpu.com/blog/2018/10/04/w… Again, welcome!
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5 years ago, everyone and his grandmother did a RISC-V core for a FPGA. Today I have the impression it is fashionable that everyone and his grandmother design a Vulcan compatible GPU for FPGA. I am very fine with that. It might push forward openXC7, the open source Xilinx tools
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Perhaps a picture would do a better job explaining what happened ... The good news is that regressions are now passing (again) following a simple fix (S/W change only) to move the sample clock earlier.
Zip CPU
@zipcpuOct 23
Today's bug: two simulators (XCelium, Icarus), same logic, one test case passes, one doesn't. Why? It's a race condition. The model sets its data on the same cycle as it gets sampled. One simulator samples the data before it gets set by the model, the other afterwards.
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Today's bug: two simulators (XCelium, Icarus), same logic, one test case passes, one doesn't. Why? It's a race condition. The model sets its data on the same cycle as it gets sampled. One simulator samples the data before it gets set by the model, the other afterwards.
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Today's bug of the week is a story. It starts with a commercial memory controller (built by yours truly), that passes all of its simulation tests. Reads tested, writes tested, WRAP tested, Exclusive access checked, etc. Many, but not all components were formally verified.
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Formally verifying the components involved required building proper interface property sets--to make sure any input assumptions were guaranteed by the prior component and so on. In the process, another bug was found whereby reads (or writes) crossing different devices might get merged. Likewise, reads might have accidentally merged requests across WRAP requests--turning WRAP requests of the H/W into hybrid WRAP requests--even though not all memories support hybrid wrap.
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Sadly, this was a "working" IP. There was no time (or money ...) planned in the schedule for rebuilding critical components. Time had to be made, but that will push everything else a bit later. I was supposed to be working on a memory controller for another type of memory. Life happens.
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I can't say I've never made this mistake before Note that TFR_WRITE != TFR_TXPARITY ... otherwise this might've worked accidentally ...
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Just for context, r_transfer is the name of the state variable -- although the bug would still be a bug either way.
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This weeks design puzzle has been to build an AXI cache: AXI in, AXI out with all WSTRB bits set. I've been a bit surprised at the requirements of such a controller, and the more I've dug into it, the more challenging and complex it becomes.
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One subtle reality, is that the two streams (read/write) of such a cache cannot be independent. If nothing else, they will need arbitration to access tag memory. This is in contrast to most of my AXI work, where I try to keep the read/write FSMs as independent as possible.
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Further, because this is intended to be an ASIC design, all cache accesses--both tag and memory--will be single port only, for area reduction purposes. That's just a sample of some sticky details.
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This stack exchange post has a good description of the problems with using AES-CTR for memory encryption. I love the included pictures. They tell the story well. crypto.stackexchange.com/que…
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Whoever thought AES-CTR could be used to secure memory ... is offering an expensive encryption that looks good but offers zero security.
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One of the differences between ASIC and FPGA design is the initial statement. ASICs don't support them. To build IP that works across technologies, I've had to be very careful where, when, and how I use such statements. In many cases, I've had to remove them over time when my FPGA designs later become ASIC designs.
IC Freely 🇨🇦@intothefloydSep 16
Replying to @zipcpu
They don't, as long as you define their initial state in register declaration to avoid X's in simulation, and of course to get the initial state that you want, whether 0 or 1.
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Arguably, the impact of any initial statements within a design on tainting any simulation results is a very real and valid threat to verifying any would-be ASIC IP, so I get their point.
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In the end, I just had to swallow my pride, say, "Yes, sir! That's a good catch. I'll fix it right away," and then go on with generating a new release. Yes, I knew the first release would've worked, but no one wanted to take that chance on simple trust.
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