Basil Nabi

Architect Labs is excited to be a part of this! AI & mathematics will have a large impact on all engineering disciplines, including chip design. We're looking forward to seeing what open problems get solved 👀

The world needs far more chip designs than the industry can produce today. AI workloads change every few months, and they are spreading beyond data centers into robotics, defense, wearables, and nearly every device around us. The silicon underneath still takes years and hundreds of millions of dollars to build, and the expertise to do it sits with a few hundred people at a handful of companies. That gap is why @architectlabs exists. In a new @DanielNenni (semiwiki) feature, our co-founders @axi_master and @aadityasubedi_ share the company's vision to reimagine how the world gets from software to silicon. We are building an end-to-end AI system that designs and verifies chips, so any organization or sovereign nation with a demanding workload can co-design the hardware towards the industry's path to superintelligence. Read the full piece in the thread:

The industry narrative says AI is transforming chip design. The data says otherwise. The industry has been adopting RTL copilots, DV agents, PD optimizers, and companies claim 3x, 10x, even 400x speedups on individual tasks. Yet first-silicon success rates have fallen to a 20-year low, and spec-to-silicon timelines have barely moved. Task-level wins are not translating into program-level outcomes. Yesterday at #DAC2026, our CEO @axi_master and Head of IP, @ekinthesumbul shared why, and what we're doing about it. Rather than bolting AI to current design flows, we at @architectlabs have built a new way of designing and verifying chips in the age of AI. It is a unified stack spanning models, specialized agents, accelerated-EDA tools, and new design methodologies, all built to empower the Human Architect to drive a design end-to-end, from software to silicon in a fraction of today's timelines. We believe more and more companies will design their own custom chips, co-designed with their workloads and our AI system will not just write RTL. It will co-design the whole stack from software to silicon: firmware, kernels, RTL, and eventually the AI models and workloads themselves. Today, Final Day of DAC 2026, Stop by our booth to see a live demo of our AI system autnonomously designed, verified, and deployed an AI acclerator it can run on. #DAC2026 #AI #ChipDesign #Semiconductors

Sneak peek into a project our research team has been working on. In an experiment, we post-trained an open-source model for RTL design, using RLVR. The primary objective was to ensure functional correctness by actually compiling and simulating the Verilog. The result, Architect v0.1, matches the closed-source frontier, Claude Opus 4.6 at the time of the experiment, and beats GPT-5.4 on the non-agentic CVDP (Comprehensive Verilog Design Problems) benchmark from NVIDIA Research. In this experiment, no agent harness or test-time scaling methods were used, and rather it was to show hillclimbing using curriculum learning and reward shaping with a limited dataset.