co-founder @architectlabs ✶ 20 #dyodd
California, USA
Joined December 2024
- Tweets59
- Following457
- Followers1.1K
- Likes3.6K
Pinned Tweet
1 year ago, it wasn't clear AI could reliably design an adder.
With today's post, its clear that in a year, the entirety of chip design, from specification to silicon, will be automated.
We show up every day to make that dream come true.
architectlabs.com/careers
We gave our AI system a spec, and in under 2 weeks, it designed, verified, and deployed a chip that beats NVIDIA.
It’s built for low-power physical AI workloads. We’re running live inference on >B+ parameter models like Llama, Qwen, and Kimi, serving at 3.4x better perf/watt than NVIDIA Jetson.
From just a specification, our AI system autonomously generated all of the RTL Design, UVM verification, formal proofs, firmware, drivers, and kernels, co-designing the model, software and silicon as one optimization loop.
Better AI can now design better chips to run AI, leading to a loop of recursive-self improvement towards our path to abundant intelligence.
Readers added context they thought people might want to know
Architect Labs did not manufacture a physical chip; the design was tested on a commercial AMD Versal FPGA board. Furthermore, the 3.4x perf/watt gain over NVIDIA Jetson is a simulation-based projection for a future 8nm ASIC, not a physical benchmark. businessinsider.com/architect-labs… architectlabs.com/architect-labs…
Ebrahim H retweeted
We're excited to announce Pathfinder's $16M in funding with our Series A led by Portage with participation from Reach Capital, Gradient and Stand Together Ventures Lab
If this animates and excites you, we're hiring: pathfindercard.com/join
Ebrahim H retweeted
Excited to announce Volantis's $88M Series A.
We are solving Al's memory bottleneck by using optics, enabling chips with huge amounts of fast & cheap memory.
By boosting both the memory bandwidth and capacity per chip by orders of magnitude, we enable ultra-fast inference (up to 10,000 tps/user) for large models (>10T) - with low $/tok to boot.
Initially, this will enable insanely fast agents - think coding agents that finish in minutes or even seconds instead of hours.
More excitingly, optics is a fundamentally scalable way to increase memory systems. Not 2X/year, but by orders of magnitude across new generations. This will enable a structurally new Al industry, including restarting scaling laws, holding entire repos in context windows & more.
Our team has pioneered many core semiconductor technologies: the 1st CoWoS product, early HBM, the 1st silicon photonics CPO systems, the 1st high volume tunable VCSELs, the 1st processors to directly communicate using light & more.
We’ve already sent data >10× farther than equally tiny electrical wires inside a chip package. Our next iteration is already taped out and targets world-record bandwidth density over relevant distances, read more: volantissemi.ai/news-insight…
Ebrahim H retweeted
Jeff Dean says:
"if you speed up chip design loops enough for RL to search them, you can compress the entire design cycle — 10 people in 3 months instead of 150 people and 2 years"
That means more specialized hardware and shorter compute bets, shrinking from 2-6 years to 6 months-4 years
Ebrahim H retweeted
been saying this for a while.
every good company will look like the quant shops.
the quant shops look like that because they operate in markets dominated by machines.
soon, all of us will operate in markets dominated by machines.
The Navier Stokes proof drama is good foreshadowing for what happens / becomes important in the entire economy going forward: spotting opportunities, pointing models at them, and validating solutions faster than others. In other words, the economy / knowledge discovery increasingly looks like quant trading / pod shops / HFs, where having a differentiated view of why an opportunity is valuable and/or realizing that an opportunity is valuable (and that it can be plausibly captured/exploited) faster than others is all that matters.
This is from a piece I wrote in October 2025 and I think it will continue to hold a lot of explanatory power.
Ebrahim H retweeted
We partnered with @AnthropicAI @OpenAI
to host the world's first math hackathon.
40 hours, $2M compute - solve, understand, and present an open problem.
Applications are live: mathathonchallenge.com
Ebrahim H retweeted
A few @Caltech friends and I are hosting the first math hackathon with frontier labs/startups.
We're giving $1M+ of compute to 100 teams to solve the hardest open problems -- competitors range from IMO golds to frontier/neolab folks to math PhDs/profs.
DM me if your company wants to be involved :) we are launching soon.
🧐
Design labor, not fab capacity, is what gates new silicon. If agents write RTL, the loop from idea -> bitstream -> running hardware collapses to something like a software release cycle.
Reconfigurable silicon stops being a compromise and becomes the fast path: you iterate architectures in days instead of committing to one for years.
Ebrahim H retweeted
Not sure if legit
but nothing about this is impossible
We gave our AI system a spec, and in under 2 weeks, it designed, verified, and deployed a chip that beats NVIDIA.
It’s built for low-power physical AI workloads. We’re running live inference on >B+ parameter models like Llama, Qwen, and Kimi, serving at 3.4x better perf/watt than NVIDIA Jetson.
From just a specification, our AI system autonomously generated all of the RTL Design, UVM verification, formal proofs, firmware, drivers, and kernels, co-designing the model, software and silicon as one optimization loop.
Better AI can now design better chips to run AI, leading to a loop of recursive-self improvement towards our path to abundant intelligence.
Readers added context they thought people might want to know
Architect Labs did not manufacture a physical chip; the design was tested on a commercial AMD Versal FPGA board. Furthermore, the 3.4x perf/watt gain over NVIDIA Jetson is a simulation-based projection for a future 8nm ASIC, not a physical benchmark. businessinsider.com/architect-labs… architectlabs.com/architect-labs…
We had to build something similar for our AI systems to autonomously improve firmware and kernels live on real FPGA racks! AI controlling hardware across all scientific domains is the future.
Today, we're kicking off the first phase of the research preview for Model Hardware Standard (MHS): a new standard for AI agents to safely operate physical equipment in scientific research and advanced manufacturing.
Read more: anthropic.com/news/model-har…
Ebrahim H retweeted
2 weeks from initial idea to fully verified, deployed, and end-to-end working RTL. All the code for the ASIC is done, and we've shown a sample of it running on FPGA. We're working hard to bring it to GDS and take it to TSMC. Read more below:
We gave our AI system a spec, and in under 2 weeks, it designed, verified, and deployed a chip that beats NVIDIA.
It’s built for low-power physical AI workloads. We’re running live inference on >B+ parameter models like Llama, Qwen, and Kimi, serving at 3.4x better perf/watt than NVIDIA Jetson.
From just a specification, our AI system autonomously generated all of the RTL Design, UVM verification, formal proofs, firmware, drivers, and kernels, co-designing the model, software and silicon as one optimization loop.
Better AI can now design better chips to run AI, leading to a loop of recursive-self improvement towards our path to abundant intelligence.
Readers added context they thought people might want to know
Architect Labs did not manufacture a physical chip; the design was tested on a commercial AMD Versal FPGA board. Furthermore, the 3.4x perf/watt gain over NVIDIA Jetson is a simulation-based projection for a future 8nm ASIC, not a physical benchmark. businessinsider.com/architect-labs… architectlabs.com/architect-labs…
Ebrahim H retweeted
Incredible, congrats guys! This is the future
We gave our AI system a spec, and in under 2 weeks, it designed, verified, and deployed a chip that beats NVIDIA.
It’s built for low-power physical AI workloads. We’re running live inference on >B+ parameter models like Llama, Qwen, and Kimi, serving at 3.4x better perf/watt than NVIDIA Jetson.
From just a specification, our AI system autonomously generated all of the RTL Design, UVM verification, formal proofs, firmware, drivers, and kernels, co-designing the model, software and silicon as one optimization loop.
Better AI can now design better chips to run AI, leading to a loop of recursive-self improvement towards our path to abundant intelligence.
Readers added context they thought people might want to know
Architect Labs did not manufacture a physical chip; the design was tested on a commercial AMD Versal FPGA board. Furthermore, the 3.4x perf/watt gain over NVIDIA Jetson is a simulation-based projection for a future 8nm ASIC, not a physical benchmark. businessinsider.com/architect-labs… architectlabs.com/architect-labs…
Ebrahim H retweeted
This is an incredible feat, the future of hardware engineering is here, and it appears that it comes down to comprehensive evaluation suites for agents to design and test hardware designs
Tldr: don’t build hardware, build the tools for agents to verify their hardware
We gave our AI system a spec, and in under 2 weeks, it designed, verified, and deployed a chip that beats NVIDIA.
It’s built for low-power physical AI workloads. We’re running live inference on >B+ parameter models like Llama, Qwen, and Kimi, serving at 3.4x better perf/watt than NVIDIA Jetson.
From just a specification, our AI system autonomously generated all of the RTL Design, UVM verification, formal proofs, firmware, drivers, and kernels, co-designing the model, software and silicon as one optimization loop.
Better AI can now design better chips to run AI, leading to a loop of recursive-self improvement towards our path to abundant intelligence.
Readers added context they thought people might want to know
Architect Labs did not manufacture a physical chip; the design was tested on a commercial AMD Versal FPGA board. Furthermore, the 3.4x perf/watt gain over NVIDIA Jetson is a simulation-based projection for a future 8nm ASIC, not a physical benchmark. businessinsider.com/architect-labs… architectlabs.com/architect-labs…
Ebrahim H retweeted
The time for AI-designed chips has arrived.
We gave our AI system a spec, and in under 2 weeks, it designed, verified, and deployed a chip that beats NVIDIA.
It’s built for low-power physical AI workloads. We’re running live inference on >B+ parameter models like Llama, Qwen, and Kimi, serving at 3.4x better perf/watt than NVIDIA Jetson.
From just a specification, our AI system autonomously generated all of the RTL Design, UVM verification, formal proofs, firmware, drivers, and kernels, co-designing the model, software and silicon as one optimization loop.
Better AI can now design better chips to run AI, leading to a loop of recursive-self improvement towards our path to abundant intelligence.
Readers added context they thought people might want to know
Architect Labs did not manufacture a physical chip; the design was tested on a commercial AMD Versal FPGA board. Furthermore, the 3.4x perf/watt gain over NVIDIA Jetson is a simulation-based projection for a future 8nm ASIC, not a physical benchmark. businessinsider.com/architect-labs… architectlabs.com/architect-labs…
Ebrahim H retweeted
The future of hardware and software co-design will be wild.
We gave our AI system a spec, and in under 2 weeks, it designed, verified, and deployed a chip that beats NVIDIA.
It’s built for low-power physical AI workloads. We’re running live inference on >B+ parameter models like Llama, Qwen, and Kimi, serving at 3.4x better perf/watt than NVIDIA Jetson.
From just a specification, our AI system autonomously generated all of the RTL Design, UVM verification, formal proofs, firmware, drivers, and kernels, co-designing the model, software and silicon as one optimization loop.
Better AI can now design better chips to run AI, leading to a loop of recursive-self improvement towards our path to abundant intelligence.
Readers added context they thought people might want to know
Architect Labs did not manufacture a physical chip; the design was tested on a commercial AMD Versal FPGA board. Furthermore, the 3.4x perf/watt gain over NVIDIA Jetson is a simulation-based projection for a future 8nm ASIC, not a physical benchmark. businessinsider.com/architect-labs… architectlabs.com/architect-labs…