CryptoMcap

Sunday Brief – Sep 20, 2026 Brief Summary On TatsuOS, a user can now go from a plain-English description of what they want a device to do, to that device running, without touching a toolchain at any point. The newest hardware family flashes straight from a browser over a USB cable, with no programmer. On the chip side, the validation pipeline that miners are scored by is complete and running on the real EDA server. The scored workloads moved from our own small models to the industry's standard benchmark suite, and our reference NPU now runs all four of those benchmarks where a week ago it ran one. TatsuOS - A user describes what they want the device to do in one sentence. The Model Assistant picks a model from our catalog that is already known to work, and the firmware flashes from Chrome. No toolchain, no programmer, no command line. - The STM32F401 is the newest supported family and the simplest to flash. It has a USB bootloader built into the chip, so there is no ST-Link, no JTAG probe and no adapter. Hold one button, tap reset, click Flash in the browser. - Devices ship configured. WiFi, broker and sensor settings are written into the firmware image at flash time, so each unit boots with its own setup and we do not build separate firmware for every device. - Custom model generation stays in development behind a gate. Recommending a model that already works is live because it is the reliable half. Generating new code means compiling it, fitting it into kilobytes and catching errors first, and that is where the cost and the risk sit. Chip Design Team - Last week we said the next step was not making our reference NPU faster, but widening the operation set, measuring baselines across the full model suite, and deciding which models are scored every time and which rotate. All three are now done. - The scored set is the four MLPerf Tiny benchmarks from MLCommons: keyword spotting, image classification, visual wake words and anomaly detection. These are four different workloads, and they are what the industry uses to compare chips in our class. Four further models sit in a rotating audit set. - Our reference NPU now runs all four correctly, where last week it ran one. Widening it to handle the full suite was the main design work of the week. - On the wider suite it falls short of the required speedup and is rejected by its own gate. It was built around convolution, and our own models were all the same shape as each other, which hid the gap. The weakest case is keyword spotting, where most of the arithmetic uses an operation we do not accelerate. Adding that operation is the next piece of work, and it appears in three of the four benchmarks. - The pipeline is complete and verified end to end on the real EDA server. The scoring package is fixed and checksummed, so every validator is running exactly the same code, models and settings, and any result can be re-run and checked against the recorded one. - Verifying it found four scoring bugs, all fixed before they could affect a miner. Clock speed was being recorded as a fixed number instead of measured. A design that did nothing at all could pass the performance gate. A miner's self-test used a different benchmark than the one scoring them, so a design could pass locally and still be rejected on submission. And a healthy hour-long evaluation was being cut short and reported as a server fault. Each fix is now covered by a test that runs before any release can be built.